MIPS 處理器 數據通路設計 verilog代寫

EECE 3324
Computer Architecture and Organization
Final Project
MIPS Architecture Implementation
Due on Apr. 14th (M) 11:59pm
Basic project: single-cycle MIPS architecture implementation (worth 25% of the total course points)
1. Overview
For the EECE3324 project, you will implement the standard single-cycle MIPS architecture in Verilog. You are given a memory Verilog file which contains both text (program instructions) and data, you should write a processor Verilog file which contains all the modules for the processor datapath and controller. The processor module interacts with the memory module. You should write your own testbench file to simulate the processor and memory. Finally, you should calculate the CPI of the provided program from the Verilog simulator.
全优代写 - 北美Essay代写,Report代写,留学生论文代写作业代写 I recommend using Modelsim as the HDL simulator. Instruction file on Modelsim installation and usage have been posted on BB. You can also use others, like ISE simulator, vcs, etc., if you are familiar with them. However, you have to let the TA and me

histogram equalization verilog代寫

ECE 464/520: Project Technical Requirements
You are to produce a Histogram Equalization Unit for image processing. A general description of what a histogram equalization unit does can be found on Wilkipedia amongst other sources,
You will be processing a series of small (640 x 480 pixel ) images. The images will contain 32-bit unsigned pixels representing gray scale images. A basic description of the algorithm is found below (this is extracted from a requirements document in one of our research projects.
Change (Feb 6, 2014). The data supplied to you actually has a dynamic range of only 8 bits per pixel. SO that you can all take advantage of this, you only need to produce a histogram where the value of each pixel is sorted into L=28 buckets, not 216 buckets.


You have to design a unit that maximizes the number of images that can be processed per unit area. You thus need to report how long (in seconds) it takes to process an image, and what is the cel

FIFO設計 verilog代寫



全优代写 - 北美Essay代写,Report代写,留学生论文代写作业代写FIFO(First In First Out)——是一種可以實現數據先入先出的存儲器件。FIFO就像一個單向管道,數據只能按固定的方向從管道一頭進來,再按相同的順序從管道另一頭出去,最先進來的數據必定是最先出去。FIFO被普遍用作數據緩沖器。



全优代写 - 北美Essay代写,Report代写,留学生论文代写作业代写同步FIFO整體架構:

解釋與說明:上圖中最大的矩形框所包圍的內部部分為所設計的同步FIFO,由FIFO主控體和RAM構成。FIFO主控體接收來自外部的讀寫控制信號(read_n,write_n)、復位信號(reset_n)和時鐘信號(clock),并在時鐘上升沿到來時根據從RAM返回的counter信號進行讀寫控制判斷以及讀寫指針的計算,并將所得結果以mwrite_n,mread_n,wr_pointer ,rd_pointer信號的形式傳遞給RAM進行相應的讀寫操作。其中counter信號代表RAM體內已存儲未讀數據的數據個數。整個同步FIFO包括八條外部數據信號線(包括總線)和五條內部數據信號線。




全优代写 - 北美Essay代写,Report代写,留学生论文代写作业代写程序開始先進行復位判斷,假如復位鍵按下,則進行復位。接著判斷讀信號是否有效,假如無效,則判斷寫是否有效,假如有效,并且存儲體不滿的話則進行寫操作,先產生正確的寫指針,然后將輸入的數據寫入對應的RAM空間內。讀雷同。當讀寫都有效時,counter不做更改,而直接產生讀寫指針,然后進行讀寫操作,當然在讀寫之前要先判斷是否空滿。

cache設計 verilog代寫

全优代写 - 北美Essay代写,Report代写,留学生论文代写作业代写In this assignment, you will design a generic memory block and use it to perform various tasks.


Part 1: Memory/cache design.

A physical cache block is made up of memory cells which are associated in rows and columns. Each row corresponds to a cache-line, which may contain any size of data. These lines are then stacked in column form. In general, each cache line consists of 3 major parts, the ID tag, the data, and the state (or status) of each line. The state bits will be ignored for this assignment (just use ID tag and data).

When a request comes in for a line, the cache lines are searched concurrently to determine if a line matches the requested ID tag. If the tag matches, then the bits in the data portion of the cache line are sent out of the system. (Note: this assignment is a scaled down version of a traditional fully-associative cache, not including any sense amplifiers and other support circuitry).

Your job is to design such a cache, with a compile-time vari